In the design of circuit boards to which electronic components connect, signal lines, such as address bus lines, may be etched in internal layers of a circuit board. The electronic components that are disposed on the circuit board and connect to the signal lines, preferably, are packed on the surfaces of the circuit board in a space efficient manner. This packing of electronic components on a circuit board is done in light of certain physical and electrical considerations.
The physical considerations are the size of the circuit board, the size of the electronic components that are to be attached to the circuit board, and the area of the circuit board that is available for etching the signal lines.
With regard to electrical considerations, it is desirable that each etch line has as minimal as possible an effect affect on the signal characteristics of the overall design. Thus, the designer attempts to minimize the number of etch lines and minimize the length of any etch lines that are needed. One method to accomplish this is to provide etch lines with common connection nodes to which the number of electronic components may connect.
It is also desirable electrically to minimize the length of the lines (stubs) that are used connect electronic components to a common connection node. Furthermore, it is desirable that the stubs that connect to a particular common connection node be symmetrical.
Another electrical consideration is the desire to minimize the capacitive loading that is caused by vias. Each via impacts the signal on the etch line to which it connects by introducing a capacitive load similar to that of an actual component. This degrades the propagation of the signal along the etch line. Therefore, the number of vias is preferably minimized, and number of components that connect to a single via is the highest possible number considering the physical constraints of the circuit board and the components that attach to it.
Generally, there are two conventional methods of packing electronic components on a circuit board. These are to use a 2-dimensional approach or a simple 3-dimensional approach. Referring to FIG. 1, an example for laying out an area of tightly coupled electronic components, such as static random access memories ("SRAMs"), using the conventional 2-dimensional approach is shown. In this Figure, SRAMs 101, 102, 104, and 106 are mounted on circuit board 100. Circuit board 100 has etch lines 108, 110, 112, 114, 116, and 118 etched in it. In a representative fashion, etch line 108 connects to pin 1 of SRAM 101 at connection 120, connects to pin 1 of SRAM 102 at connection 122, connects to pin 1 of SRAM 104 at connection 124, and connects to pin 1 of SRAM 106 at connection 126. In like manner, etch line 110 connects to pins 2 of the SRAMs, etch line 112 to pins 3 of the SRAMs, etch line 114 to pins 4 of the SRAMs, etch line 116 to pins 5 of the SRAMs, and etch line 118 to pins 6 of the SRAMs.
When the 2-dimensional approach is used, the packing of electronic components depends on the size of the components, such as the SRAMs shown in FIG. 1. The closest that a connection point of one electronic component may be to the connection point of another component is the width of a component. It is also seen that the length of the etch line depends on the specific number of electronic components that are connected to circuit board 100.
A major disadvantages of the 2-dimensional approach is that the etch line will be considerably long. As such, there will be a significant delay associated with accessing the electronic components that are at, or near, the end of a row or column of electronic components.
FIGS. 2 and 3 show circuit board 200 that employs the conventional 3-dimensional approach for packing electronic components, such as SRAMs 201, 202, 204, 206, and 301 and the SRAMs that are disposed opposite SRAMs 202, 204, and 206 which are not shown. According to the conventional 3-dimensional approach, the SRAMs are connected to both planar surfaces of circuit board 200. Etch lines 208, 210, 212, 214, 216, and 218, which may be address lines, are etched in predetermined layers of circuit board 200.
Representative etch line 208 connects to common connection node 220. Common connection node 220 connects to via 302 that extends between the two planar surfaces of circuit board 200. Common connection node 220 connects to pin 1 of SRAM 201 at 306 through via 302 and stub 304, and connects to pin 1 of SRAM 301 at 312 through via 302 and stub 310.
In FIG. 2, the representative common connection nodes to which two SRAMs connect are nodes 220, 222, 224, and 226. It is understood that these nodes are representative of all of the nodes shown in FIGS. 2 and 3.
The conventional 3-dimensional approach has several advantages over the 2-dimensional approach. By using both planar surfaces of circuit board 200, the capability exists to decrease the length of the etch line by one half. It also provides for symmetrical stub lengths for the two SRAMs connected to a common connection node, such as node 220. However, this conventional 3-dimensional approach still has far too many vias.
The present invention solves these and other problems as will be set forth in the remainder of the specification referring the attached drawings.